// mvp Version 2.24
// cmd line +define: MIPS_SIMULATION
// cmd line +define: MIPS_VMC_DUAL_INST
// cmd line +define: MIPS_VMC_INST
// cmd line +define: M14K_NO_ERROR_GEN
// cmd line +define: M14K_NO_SHADOW_CACHE_CHECK
// cmd line +define: M14K_TRACER_NO_FDCTRACE
//
// 	Description:  m14k_cache_mux
// 	     Cache way select mux logic
//	
//	$Id: \$
//	mips_repository_id: m14k_cache_mux.mv, v 1.1 
//


//	mips_start_of_legal_notice
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//	

`include "m14k_const.vh"
module m14k_cache_mux(
	data_in,
	waysel,
	data_out);


	/* parameters */

	// synopsys template
	parameter		WIDTH=1;		// WIDTH of Data per Way
	parameter		ASSOC=1;		// Cache Associativity


	/* Inputs */
	input [ASSOC*WIDTH-1:0]	data_in;		// Output from cache data ram
	input [3:0]		waysel;		// Comparison flags coming out of cache_cmp

	/* Outputs */
	output [WIDTH-1:0]	data_out;	// Selected Data

// BEGIN Wire declarations made by MVP
wire [WIDTH-1:0] /*[0:0]*/ data_out;
wire [ASSOC*WIDTH-1:0] /*[0:0]*/ wide_data_out;
// END Wire declarations made by MVP


	/* End of I/O */

	assign wide_data_out [ASSOC*WIDTH-1:0] = 	{ WIDTH {waysel[0]}} & data_in | 
		  	 	{ WIDTH {waysel[1]}} & (data_in >> WIDTH) | 
		  		{ WIDTH {waysel[2]}} & (data_in >> (WIDTH * 2)) | 
		              	{ WIDTH {waysel[3]}} & (data_in >> (WIDTH * 3));

	assign data_out [WIDTH-1:0] = wide_data_out[WIDTH-1:0];
	

endmodule // m14k_cache_mux

